1. Field of Invention
The present invention relates to a method for controlling impurity density distribution in a semiconductor device, in particular to one that makes different regions have different impurity concentrations in the same doping process. The present invention also relates to a semiconductor device which is made by the method.
2. Description of Related Art
In manufacturing a semiconductor device, a doping process is often used to change the property of a semiconductor material so that it fits the requirements for device operation. Typically, a photolithography or self-align process is used to define a doped area, and an ion implantation process is performed to dope impurities. In the prior art, the implantation dosage and acceleration voltage within the same doping process are the same, and therefore, if there are different regions which require different doping concentrations, the only way is to perform another doping process to dope a different area defined by a different mask.
FIG. 1 shows, by cross-section view, a prior art laterally diffused metal oxide semiconductor device (LDMOS device), wherein the LDMOS device is formed by the following semiconductor processing steps: first, implanting N-type impurities into a substrate 11 by ion implantation to form an N-type buried layer 12; next, forming an epitaxial layer on the substrate 11; then, defining a pattern for P-type well regions 13, and doping P-type impurities in the epitaxial layer by ion implantation to form the P-type well regions 13; next, defining a pattern for N-type well regions 14, and doping N-type impurities in the epitaxial layer by ion implantation to form the N-type well regions 14; then, defining a pattern for a body region 16, and doping impurities in one of the P-type well regions 13 by ion implantation to form the body region 16; next, forming a shallow trench isolation (STI) region 15; then, defining patterns for P-type heavily doped regions 17 and N-type heavily doped regions 18 respectively, and doping N-type impurities and P-type impurities by ion implantation to form the P-type heavily doped region 17 and the N-type heavily doped region 18 respectively; Lastly, forming a gate structure 19. In the prior art mentioned above, because one single mask and one single ion implantation process are used to form the N-type buried layer 12, the impurity concentrations are the same in the region which contacts with the P-type well region 13 and the regions which contact with the N-type well region 14. The body region 16 is located in the P-type well region 13 which contacts with the N-type buried layer 12; in a normal operation mode of the LDMOS device, the body region 16 is coupled to a relatively high voltage, and thus breakdown may occur more easily between the P-type well regions 13 and the N-type buried layer 12 than in other regions.
With the reduction in the size and the increase in the operating voltage of the device, a higher breakdown voltage is required to prevent breakdown in the prior art mentioned above. Thus, according to some prior art, the dosage of ion implantation to form the N-type buried layer 12 is reduced, to provide a higher breakdown voltage. However, the contact resistance between the N-type buried layer 12 and the N-type well regions 14 would increase accordingly, and the effect of isolating the device and the substrate by the N-type buried layer 12 would be limited. The application of such device is also limited.
Besides the above, in some cases it may be required to implant a relatively low impurity concentration in making a semiconductor device, but due to hardware restriction of the ion implanter equipment, an ion beam with such low dosage can not be generated, and thus it is not possible to provide such low concentration implantation.
In view of the above, the present invention proposes a method for controlling impurity density distribution in a semiconductor device, and a semiconductor device which is made by the method to overcome the drawbacks in the prior art.